Maskless Photolithography

Update 8/26/17: Developing Patterning Process for Homemade Microelectronics

The general idea is to use a modified presentation projector and reduction optics to transfer an image to the photoresist on a wafer without the use of expensive masks. Below are descriptions of the 4 iterations of my photolithography setups:

Mark IV:

Automated DLP submicron stepper for 2″ (50mm) wafers with LabView control, computer alignment, and wafer vacuum chuck

Stepped array
Stepped array

The second and third images above are composed of 4 precisely aligned exposures which enables submicron resolution over large areas. This “true” stepper operation uses a closed-loop feedback system and computer visual alignment.

SEM image
SEM image
Metal
Metal

Mark III:

Manual LCoS submicron stepper with red laser alignment illumination. Given a numerical aperture of 0.98 on the microscope objective and with an exposure wavelength of 365nm the simple calculated resolution is 0.227um however the actual resolution is probably around 0.5um due to diffraction limitations inherent in this projection system. The depth of focus @ NA = 0.98 is calculated to be approximately 1.8um but is likely worse.

Mark II:

Manual DLP projection aligner >10um features. Color wheel is removed because it did not transmit much light below 400nm. Emulation (relaxation oscillator) circuits were made to reproduce the signals that the projector expected from the color wheel back EMF motor drive/sensor and photodiode.

Exposure times calculated by integration of total UV dosage measured at different wavelengths with the radiometer. To calculate exposure time for AZ4210 resist, for example, the datasheet is consulted to see a recommended dose of around 135 mJ/cm^2 for a 3.5um film thickness. If exposed with a 5x objective on my system, the exposure time @ 410nm is (135 mJ/cm^2)/(4.05mW/cm^2) = approx. 33 seconds. This is a bit longer than I would like but given that it is a positive resist that is to be expected.

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Mark I:

Proof-of-concept DLP setup

IMG_0967

 

Semiconductor Fabrication Basics – Home Chip Lab

A brief introduction to semiconductor fabrication processes and terminology. It is not intended to be an in depth view of any single process, but rather an overview so that provides enough information for someone to get started with making diodes and transistors at home.

Tour of my home chip fab setup in early 2017. I’ve been accumulating this equipment since October of 2016.

 

 

Step by step FET fabrication

 

High vacuum basics

Rewound MOT for thermal evaporation – 800amps and new Lindberg 1″ tube furnace for diffusion

rewound mot for thermal evap rewound mot for thermal evap (1) rewound mot for thermal evap (2) tube furnace

Rewound a microwave oven transformer using 1 gauge welding wire. Before saturation it puts out 1.8volts ish. I plan to use it to heat up a tungsten boat for thermal evaporation deposition. I may rewind it with slightly thinner wire so I can get more turns on the secondary and a little higher voltage. Last picture is a new/old Lindberg 1″ dia. tube furnace I got, goes up to 1400c which is crazy. I use it for diffusion of N type and P type dopants into my homemade semiconductors as well as thermal oxidation. I have a large nitrogen tank which allows me to create a nitrogen atmosphere in it during diffusion and when I want to facilitate SiO2 growth I pump steam through the furnace and turn the nitrogen flow off. I have a mass flow controller for the nitrogen but haven’t hooked it up yet.

Fabrication and Characterization of N-Channel Enhancement Mode Insulated Gate Field Effect Transistors

Update 4/25/18: First IC!

Update 8/27/17: Developing Patterning Process for Homemade Microelectronics

Update 7/30/17: Developing Metalization Process for Homemade Microelectronics

These are my first working transistors. Specifically, they are insulated gate enhancement mode n channel field effect transistors. I also made a depletion mode FET with a conducting channel and it worked even better than the enhancement mode ones. I drew out the steps I took to make this, they’re based on Jeri Ellsworth’s work but with a few main changes. It is very important that your dielectric overlap source and drain regions on the FET, otherwise no inversion layer can be formed and the FET cannot turn on. Only a small overlap is necessary and the larger it is, the more unwanted capacitance there is. This is not normally a consideration in actual production because inherent lateral diffusion takes care of the overlap but for these large hand made devices I found you have to get very lucky with your alignment if you don’t budget extra overlap.

A huge thanks to Jeri for making her videos about home chip fabrication which got me interested in these experiments in the first place.

You can see in the center of the transistor there is a red region of silicon dioxide, this is the gate and the color indicates that it is roughly 750 angstroms thick. I would like to make the gate thinner so I can achieve lower threshold voltages, etc. but it is hard to make a truly insulating gate much thinner than that in a dirty environment because of pinholes and other impurities in the oxide layer.

Diode characteristics are characterized with a semiconductor parameter analyzer

A brief introduction to semiconductor fabrication processes and terminology. It is not intended to be an in depth view of any single process, but rather an overview so that provides enough information for someone to get started with making diodes and transistors at home.

Tour of my home chip fab setup in early 2017. I’ve been accumulating this equipment since October of 2016.

Step by step FET fabrication

Oxide and Spin on Diffusant Thin Film Interference Patterns on Wafers

spin on diffusant interference patterns 4 spin on diffusant interference patterns 3 spin on diffusant interference patterns 2

spin on diffusant interference patterns 1 large wafer contamination from thermal oxide growth structure stress patterns

As of now, I am doing all of my doping with spin on diffusants. Some of which are solutions of Phosphoric/boric acid in alcohol/water that I prepared myself. I find it hard to control the dopant concentration and therefore bandgap of devices so my solar cells often have a bandgap too high or too low. I thought using an actual spin on dopant would help, so I bought some P509 phosphorus glass from Filmtronics and it works about the same as the solutions I made, except it spins on much nicer.

The colors you are seeing are contamination and nonuniformity in the thin film interference patterns caused by this thin glass layer after pre deposition of the spin on diffusants.

Continue reading Oxide and Spin on Diffusant Thin Film Interference Patterns on Wafers

Silicon Wafer Pics – Thermal Oxidation

50mm wafers 3 Copper 8_ wafer

 

moisture on 50mm wafer 500nm oxidation macro50mm wafer 500nm oxidation macro(5)

Blue color indicates roughly 500nm SiO2 thickness. It took about 2.5hours to grow @ 1200c in a pottery kiln style furnace with steam being pumped into it. Picture above on the left shows moisture on cooling wafer. Picture on the right shows unpolished backside of the wafer. Notice the nonuniformity in the growth thickness caused by unequal heating. This is because I don’t have a quartz boat to hold the wafers so I place them face up in the furnace.  Continue reading Silicon Wafer Pics – Thermal Oxidation