Blue color indicates roughly 500nm SiO2 thickness. It took about 2.5hours to grow @ 1200c in a pottery kiln style furnace with steam being pumped into it. Picture above on the left shows moisture on cooling wafer. Picture on the right shows unpolished backside of the wafer. Notice the nonuniformity in the growth thickness caused by unequal heating. This is because I don’t have a quartz boat to hold the wafers so I place them face up in the furnace. Continue reading Silicon Wafer Pics – Thermal Oxidation
First pictures show wafers with 5000A field oxide, then etched active region for the anode with HF. As you can see on the curve tracer, reverse bias conditions are surprisingly good with little leakage current down to -6 volts.
Testing of homemade solar cells/PN junction diodes. Some of them output up to .25v open circuit and a few hundred microamps at short. This varies widely because of changes in dopant concentration and wafer size. The higher dopant concentration makes a lower bandgap. Most of these devices have a band gap that is too low to be most efficient for a solar cell. Optimally I would want about 1.4ev. As dopant concentration increases, the wave functions that describe the electrons in both valence and conduction bands start to converge and overlap so the bandgap basically gets broken and the solar cells preform very poorly. I estimate about 1% efficiency on these cells, most likely less.
I wanted to try anodic oxidation because it would allow me to grow SiO2 dielectric layers much quicker and also at room temperature. The result, while using potassium nitrate solution, was a very dirty growth later that would only be suited for a field oxide on a diode and far from precise enough for a gate oxide on a FET. Possibly with more refining in the future this could save me a lot of time waiting for furnaces to heat up.
This wafer has an un patterned copper metalization layer.
Monocrystalline wafers with a known crystal orientation (<100> in this case) can be easily cleaved into small squares (or triangles, depending on the orientation). Traditionally, <100> wafers are used for CMOS/FET devices and <111> wafers are used for bipolar devices. Thermal oxidation, SiO2 etching, and carrier mobility can greatly differ based on orientation. I believe 100 wafers have lower hole mobility than <110> and <111>. <111> wafers have the highest packing density. <100> wafers allow field effect devices to have lower threshold voltages. Many MEMS devices use <110> or <111> wafers.
I had the day off school due to a bomb threat so I had some extra time to work in the shop and had my first success with thermally grown SiO2. The process is very simple. At the time, I didn’t have a tube furnace so I put the wafers in a pottery kiln that went up to 1000c and poured 25ml of water into the top of the kiln through a small opening manually every 5 minutes for about 6 hours to saturate the furnace with water vapor. This wet oxidation technique allowed me to grow the field oxide for my first few semiconductor devices, diodes.