There are a number of open source layout and design tools for ICs however here I will just focus on Magic VLSI. Below are the steps to take a design from Verilog through synthesis and layout to the physical mask that is used for fabrication, via the Qflow digital synthesis flow.
The Verilog digital design for this example is a UART interface from www.asic-world.com and is synthesized/routed with the standard SCMOS rules, however a custom .tech file can be specified containing process details and design rules for DRC.
Once Qflow executes successfully, the design can be viewed in Magic after loading the appropriate cells and a GDS file is generated. This is opened in OwlVision GDSII Viewer or similar which can be used to generate the individual mask image files for each layer (active, poly, metal, etc.)