There are a number of open source layout and design tools for ICs however here I will just focus on Magic VLSI. Below are the steps to take a design from Verilog through synthesis and layout to the physical mask that is used for fabrication, via the Qflow digital synthesis flow.
The Verilog digital design for this example is a UART interface from www.asic-world.com and is synthesized/routed with the standard SCMOS rules, however a custom .tech file can be specified containing process details and design rules for DRC.
Once Qflow executes successfully, the design can be viewed in Magic after loading the appropriate cells and a GDS file is generated. This is opened in OwlVision GDSII Viewer or similar which can be used to generate the individual mask image files for each layer (active, poly, metal, etc.)
Thermal evaporation deposition of Al and Ge from Tungsten and Tantalum boats, respectively. A blind hole is drilled and tapped in the chamber bottom plate for a center tap feedthrough (common ground) for the boats. Deposition starts at around 7e-7Torr and ends around 5e-6Torr due to outgassing. Aluminum alloys with Tungsten at the high temperature and causes boat failure, a thicker gauge boat will be used in the future or one made of TiB2-BN or BN. Update: W 0.015″ boat thickness seems OK.
Approx. deposition rate throughout the run was 2.2A/s, with total accumulation of 500A. Much faster than my sputtering setup but yields a worse film.
In situ plasma cleaning is via the red ICP coil seen in the 8th picture. A Quartz Crystal Microbalance (QCM) is used to measure the thickness of the deposited films and current is supplied by a rewound microwave oven transformer. The UV-VIS spectrometer is used to monitor the emission spectra of O2 plasma. O2 is flowed into the chamber via a Mass Flow Controller (MFC) until the pressure is 75-100mTorr and the substrate is plasma cleaned for 5 minutes with 100W RF prior to depositions.
As current pass through the boats, they heat up to 1000 – 1800C and subsequently heat up much of the surrounding chamber and mounting parts. This starts serious outgassing in the chamber and without prior cleaning and bake out quickly raises the pressure to non-workable pressures and the deposition rate slows.
I added a second turbo pump to raise the pumping speed/gas throughput (previously 110L/s and now an additional 50L/s) and to tolerate higher outgassing.
It was also noted that the evaporation of Al with lots of H2O vapor in the chamber (no baking) leads to a reduction of chamber pressure (presumably the formation of Al2O3 with H2O) and the production of H2 as seen on an RGA.
Tall particles can easily short out the thin gate oxide in these devices, as shown under my SEM. This poses an issue for making such devices in a garage; the gate oxides must be grown thicker to mitigate shorted devices which leads to a higher threshold voltage for the FET.
Recent progress into 1um feature sizes and beyond with a LCoS projector and a metallurgical microscope. Given a numerical aperture of 0.98 on the microscope objective and with an exposure wavelength of 365nm the simple calculated resolution is 0.227um however the actual resolution is probably around 0.5um due to diffraction limitations inherent in this projection system. The depth of focus @ NA = 0.98 is calculated to be approximately 1.8um but is likely worse.
Laser illumination of the projector is avoided due to interference patterns. A SMD 395nm LED is used in some tests and a standard high pressure mercury arc vapor lamp in others.
Exposure times calculated by integration of total UV dosage measured at different wavelengths with the radiometer. To calculate exposure time for AZ4210 resist, for example, the datasheet is consulted to see a recommended dose of around 135 mJ/cm^2 for a 3.5um film thickness. If exposed with a 5x objective on my system, the exposure time @ 410nm is (135 mJ/cm^2)/(4.05mW/cm^2) = approx. 33 seconds. This is a bit longer than I would like but given that it is a positive resist that is to be expected.
Basic mask set for a MOSFET. Fiducials should be added to the corners for subsequent layer alignment. Active area is etched into field oxide, active area is doped, gate oxide is etched and regrown as thin a possible without pinholes, contact area is etched into oxide, then aluminum or copper is sputtered or evaporated and patterned.
Progress in developing the metalization process for the home chip lab. DC and RF sputtering is used and the process will be refined more and then I will move on to the wet process with etching metal through resist mask, etc.
Sample is scratched with a razor and surface roughness is measured with a KLA Tencor Stylus Profiler. Surface is extremely rough and best interpretation of the data leads me to believe the thickness of the sputtered film is approximately 0.492um.
A brief introduction to semiconductor fabrication processes and terminology. It is not intended to be an in depth view of any single process, but rather an overview so that provides enough information for someone to get started with making diodes and transistors at home.
Tour of my home chip fab setup in early 2017. I’ve been accumulating this equipment since October of 2016.
Rewound a microwave oven transformer using 1 gauge welding wire. Before saturation it puts out 1.8volts ish. I plan to use it to heat up a tungsten boat for thermal evaporation deposition. I may rewind it with slightly thinner wire so I can get more turns on the secondary and a little higher voltage. Last picture is a new/old Lindberg 1″ dia. tube furnace I got, goes up to 1400c which is crazy. I use it for diffusion of N type and P type dopants into my homemade semiconductors as well as thermal oxidation. I have a large nitrogen tank which allows me to create a nitrogen atmosphere in it during diffusion and when I want to facilitate SiO2 growth I pump steam through the furnace and turn the nitrogen flow off. I have a mass flow controller for the nitrogen but haven’t hooked it up yet.