Installation of a Perkin Elmer hot cathode ionization gauge on my PVD chamber. I applied current to the filament briefly at atmospheric pressure and the filament did not burn out so it may have a yttria-coated iridium filament rather than tungsten or any other refractory element. This will be my main mid to high vacuum gauge, used in conjunction with a thermcouple gauge and a Baratron pressure traducer for backing pressure measurement. The gauge mounted up to a 2 3/4″ conflat. I have a HP 59822B ionization gauge controller which provides filament current and reads collector current and displays it in torr.
Thanks to Charles Alexanian for this additional information:
“…your assumption about your gauge is correct in that it is an iridium filament. That being said the yittria coating can be poisoned by a great many things requiring a re calibration of your system depending on which type or controller you are using. The tungsten filament versions stayed popular in chamber research because you could simply boil off anything that might condense on the filament… I have changed over my Bayard Alpert type gauges. (That is the technical term for the gauge you are showing) for inverted magnetron types, particularly the MKS903 type units because they give a analog voltage output and require no external controller. Additionally they can be easily disassembled and cleaned. The also have a higher starting pressure where I no longer need thermocouple gauges.”
The quartz thickness monitor is a Maxtek TM-100 that I picked up on ebay for under $100. The board is very corroded so after a lot of contact cleaning I was able to get it working. Displays rate in angstroms per sec and integrates to find total thickness. Surprisingly simple circuity, it’s all based around a single counter chip and of course 7 segment display drivers and such.
A brief introduction to semiconductor fabrication processes and terminology. It is not intended to be an in depth view of any single process, but rather an overview so that provides enough information for someone to get started with making diodes and transistors at home.
Tour of my home chip fab setup in early 2017. I’ve been accumulating this equipment since October of 2016.
Step by step FET fabrication
High vacuum basics
Rewound a microwave oven transformer using 1 gauge welding wire. Before saturation it puts out 1.8volts ish. I plan to use it to heat up a tungsten boat for thermal evaporation deposition. I may rewind it with slightly thinner wire so I can get more turns on the secondary and a little higher voltage. Last picture is a new/old Lindberg 1″ dia. tube furnace I got, goes up to 1400c which is crazy. I use it for diffusion of N type and P type dopants into my homemade semiconductors as well as thermal oxidation. I have a large nitrogen tank which allows me to create a nitrogen atmosphere in it during diffusion and when I want to facilitate SiO2 growth I pump steam through the furnace and turn the nitrogen flow off. I have a mass flow controller for the nitrogen but haven’t hooked it up yet.
These are my first working transistors. Specifically, they are insulated gate enhancement mode n channel field effect transistors. I also made a depletion mode FET with a conducting channel and it worked even better than the enhancement mode ones. I drew out the steps I took to make this, they’re based on Jeri Ellsworth’s work but with a few main changes. She made no mention of it in her videos but it is very important that your dielectric overlap source and drain regions on the FET, otherwise no inversion layer can be formed and the FET cannot turn on. Only a small overlap is necessary and the larger it is, the more unwanted capacitance there is. I will make YouTube videos as soon as I have time that go into more detail about how I made it and also show the device’s characteristics.
A huge thanks to Jeri for making her videos about home chip fabrication which got me interested in these experiments in the first place.
You can see in the center of the transistor there is a red region of silicon dioxide, this is the gate and the color indicates that it is roughly 750 angstroms thick. I would like to make the gate thinner so I can achieve lower threshold voltages, etc. but it is hard to make a truly insulating gate much thinner than that in a dirty environment because of pinholes and other impurities in the oxide layer.
Step by step fab video
As of now, I am doing all of my doping with spin on diffusants. Some of which are solutions of Phosphoric/boric acid in alcohol/water that I prepared myself. I find it hard to control the dopant concentration and therefore bandgap of devices so my solar cells often have a bandgap too high or too low. I thought using an actual spin on dopant would help, so I bought some P509 phosphorus glass from Filmtronics and it works about the same as the solutions I made, except it spins on much nicer.
The colors you are seeing are contamination and nonuniformity in the thin film interference patterns caused by this thin glass layer after pre deposition of the spin on diffusants.
Blue color indicates roughly 500nm SiO2 thickness. It took about 2.5hours to grow @ 1200c in a pottery kiln style furnace with steam being pumped into it. Picture above on the left shows moisture on cooling wafer. Picture on the right shows unpolished backside of the wafer. Notice the nonuniformity in the growth thickness caused by unequal heating. This is because I don’t have a quartz boat to hold the wafers so I place them face up in the furnace. Continue reading Silicon Wafer Pics – Thermal SiO2 Growth ~500nm