Thermal Evaporation (Physical Vapor Deposition)

Thermal evaporation deposition of Al from Tungsten boat at 5.5×10^-6 Torr and around 200 amps. Aluminum alloys with Tungsten at the high temperature and causes boat failure, a thicker gauge boat will be used in the future or one made of TiB2-BN or BN.

Approx. deposition rate throughout the run was 2.2nm/s, with total accumulation of 0.5um. Much faster than my sputtering setup but yields a far worse film.

Aluminum is deposited through tin foil shadow mask onto Si wafer as a test.

Power was from a rewound MOT, current limited by resistance of copper feedthrough and connections to W boat.

Developing Patterning Process for Homemade Microelectronics

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Final process:

  • Clean/prep wafer – Piranha, RCA 1 / 2
  • Water rinse
  • Remove native and RCA oxide – 1-2% HF dip
  • Field oxide growth – 2 hours @ 1200 c w/ water vapor, 5000A blue film
  • If wafer in storage, dehydration bake – 10 min @ 220c
  • Check wafer hydrophobic if necessary
  • Optional spin HMDS
  • Spin 3.5mL AZ 4210 resist 30 sec @ 3500 rpm ~3.5um film
  • Soft bake resist 3 min @ 105c hotplate
  • Expose active area – 18 sec DLP projector
  • Develop 1:3 400k KOH:H20 puddle 2 min
  • Water rinse (no solvent)
  • Inspect wafer, if defect strip resist and retry
  • Hard bake 5 min @ 115c hotplate
  • Etch active area – 1-2% HF 10 min or until surface hydrophobic
  • Water rinse
  • Resist strip – Plasma ashing 100 watts RF 5 min @ 125mTorr O2
  • Acetone rinse
  • IPA rinse
  • Water rinse

Tall particles can easily short out the thin gate oxide in these devices, as shown under my SEM. This poses an issue for making such devices in a garage; the gate oxides must be grown thicker to mitigate shorted devices which leads to a higher threshold voltage for the FET.

Submicron Maskless Photolithography

Recent progress into 1um feature sizes and beyond with a LCoS projector and an infinity-corrected metallurgical microscope. Given a numerical aperture of 0.98 on the microscope objective and with an exposure wavelength of 365nm the simple calculated resolution is 0.227um however the actual resolution is probably around 0.5um due to diffraction limitations inherent in this projection system. The depth of focus @ NA = 0.98 is calculated to be approximately 1.8um but is likely worse.

Laser illumination of the projector is avoided due to interference patterns. A SMD 395nm LED is used in some tests and a standard high pressure mercury arc vapor lamp in others.

Screen Shot 2017-09-02 at 8.03.03 PM

Exposure times calculated by integration of total UV dosage measured at different wavelengths with the radiometer. To calculate exposure time for AZ4210 resist, for example, the datasheet is consulted to see a recommended dose of around 135 mJ/cm^2 for a 3.5um film thickness. If exposed with a 5x objective on my system, the exposure time @ 410nm is (135 mJ/cm^2)/(4.05mW/cm^2) = approx. 33 seconds. This is a bit longer than I would like but given that it is a positive resist that is to be expected.

Basic mask set for a MOSFET. Fiducials should be added to the corners for subsequent layer alignment. Active area is etched into field oxide, active area is doped, gate oxide is etched and regrown as thin a possible without pinholes, contact area is etched into oxide, then aluminum or copper is sputtered or evaporated and patterned.

Developing Metalization Process for Homemade Microelectronics

(Click on image to enlarge)

Progress in developing the metalization process for the home chip lab. DC and RF sputtering is used and the process will be refined more and then I will move on to the wet process with etching metal through resist mask, etc.

Sputtering Setup

Sample is scratched with a razor and surface roughness is measured with a KLA Tencor Stylus Profiler. Surface is extremely rough and best interpretation of the data leads me to believe the thickness of the sputtered film is approximately 0.492um.

DC Sputtering
DC Sputtering

Maskless Photolithography – DLP and LCoS

Update 8/26/17: Developing Patterning Process for Homemade Microelectronics

Update 8/14/17: Submicron Maskless Photolithography

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Semiconductor Fabrication Basics – Home Chip Lab

A brief introduction to semiconductor fabrication processes and terminology. It is not intended to be an in depth view of any single process, but rather an overview so that provides enough information for someone to get started with making diodes and transistors at home.

Tour of my home chip fab setup in early 2017. I’ve been accumulating this equipment since October of 2016.

 

 

Step by step FET fabrication

 

High vacuum basics

Rewound MOT for thermal evaporation – 800amps and new Lindberg 1″ tube furnace for diffusion

rewound mot for thermal evap rewound mot for thermal evap (1) rewound mot for thermal evap (2) tube furnace

Rewound a microwave oven transformer using 1 gauge welding wire. Before saturation it puts out 1.8volts ish. I plan to use it to heat up a tungsten boat for thermal evaporation deposition. I may rewind it with slightly thinner wire so I can get more turns on the secondary and a little higher voltage. Last picture is a new/old Lindberg 1″ dia. tube furnace I got, goes up to 1400c which is crazy. I use it for diffusion of N type and P type dopants into my homemade semiconductors as well as thermal oxidation. I have a large nitrogen tank which allows me to create a nitrogen atmosphere in it during diffusion and when I want to facilitate SiO2 growth I pump steam through the furnace and turn the nitrogen flow off. I have a mass flow controller for the nitrogen but haven’t hooked it up yet.

Fabrication and Characterization of N-Channel Enhancement Mode Insulated Gate Field Effect Transistors

Update 8/27/17: Developing Patterning Process for Homemade Microelectronics

Update 7/30/17: Developing Metalization Process for Homemade Microelectronics

These are my first working transistors. Specifically, they are insulated gate enhancement mode n channel field effect transistors. I also made a depletion mode FET with a conducting channel and it worked even better than the enhancement mode ones. I drew out the steps I took to make this, they’re based on Jeri Ellsworth’s work but with a few main changes. It is very important that your dielectric overlap source and drain regions on the FET, otherwise no inversion layer can be formed and the FET cannot turn on. Only a small overlap is necessary and the larger it is, the more unwanted capacitance there is. This is not normally a consideration in actual production because inherent lateral diffusion takes care of the overlap but for these large hand made devices I found you have to get very lucky with your alignment if you don’t budget extra overlap.

A huge thanks to Jeri for making her videos about home chip fabrication which got me interested in these experiments in the first place.

You can see in the center of the transistor there is a red region of silicon dioxide, this is the gate and the color indicates that it is roughly 750 angstroms thick. I would like to make the gate thinner so I can achieve lower threshold voltages, etc. but it is hard to make a truly insulating gate much thinner than that in a dirty environment because of pinholes and other impurities in the oxide layer.

A brief introduction to semiconductor fabrication processes and terminology. It is not intended to be an in depth view of any single process, but rather an overview so that provides enough information for someone to get started with making diodes and transistors at home.

Tour of my home chip fab setup in early 2017. I’ve been accumulating this equipment since October of 2016.

Step by step FET fabrication