SiO2 Patterning

In IC fabrication it is necessary to deposit/grow and etch insulating layers of Silicon Dioxide. This presents a few problems for standard photolithographic patterning because SiO2 is hydrophilic which can cause photoresist adhesion issues and also the HF etchant attacks most photoresists. These issues combine to leave you with poor pattern definition and often complete photoresist lift during etch. The steps I have found to mitigate these issues are (in order): dehydration bake, HMDS vapor prime, thick resist coating, and buffered oxide etch solution.

First, SiO2 is thermally grown on a test wafer using a water vapor source on a nearby hotplate to fill the furnace with steam during oxidation.


Mark IV Maskless Submicron Photolithography Stepper

Details and photos of my newest maskless photolithography stepper have been posted here: Info Page


Automated DLP submicron stepper for 2″ (50mm) wafers with LabView control, computer alignment, and wafer vacuum chuck. Based on an old Nikon microscope with custom optics and in-situ UV-VIS spectroscopy for illumination process control. Diffraction-limited resolution is <250nm with a 365nm light source.

SEM image
SEM image

Lift-Off Metal Patterning

Lift-off is a technique that allows you to patten a metal layer without any etchant chemicals. Photoresist is spun on, exposed, and developed then the metal is sputtered or evaporated on top of the resist. The photoresist is then striped and any metal on top of it is peeled off. This leaves metal in only the areas in which the resist was not present after developing.

Typically, negative photoresist is preferred for lift-off for a number of reasons but I did not want to change my existing process so I attempted it with positive AZ4210 resist yielding decent results.

Photoresist can be removed in acetone or developer solution (assuming it is exposed by ambient light during processing) but a lower vapor-pressure solvent is preferred. An ultrasonic bath can also improve lift-off.

If lift-off is difficult, a thicker resist film or thinner metal coating can help. Also, substrate heating during deposition leads to resist softening and side wall coating, making lift-off impossible. I used a Peltier cooler in my chamber to prevent this.

Silicon Wafer Laser Scribing and Cutting

Using a 50W Ytterbium fiber laser to scribe and cut Silicon wafers. Laser wavelength is 1062nm and since Silicon has poor transmission at this low IR wavelength, enough energy is absorbed to make laser marks.

Scribe marks are made at higher speed and must follow perpendicular or parallel to a flat of the <100> wafer so that the scribe lies along a crystal lattice line. When cutting all the way through the wafer, higher power is used and arbitrary shapes that do not follow the crystal lines are possible.

IC Design Tools: From Verilog to Masks

There are a number of open source layout and design tools for ICs however here I will just focus on Magic VLSI. Below are the steps to take a design from Verilog through synthesis and layout to the physical mask that is used for fabrication, via the Qflow digital synthesis flow.

The Verilog digital design for this example is a UART interface from and is synthesized/routed with the standard SCMOS rules, however a custom .tech file can be specified containing process details and design rules for DRC.

Once Qflow executes successfully, the design can be viewed in Magic after loading the appropriate cells and a GDS file is generated. This is opened in OwlVision GDSII Viewer or similar which can be used to generate the individual mask image files for each layer (active, poly, metal, etc.)

Using the same tools mentioned above, I also designed a simple PMOS chip to test my process. It is scalable to any reasonable size and contains 2 differential amplifier circuits (seen on right and middle) and a number of diodes/resistors and other test features on the left.

The design requires 4 masks for fabrication: active/diffusion, gate oxide, contact, and metal.

Fiducials should be added for subsequent layer alignment. Note: Grateful Dead bears are necessary for the circuit to function correctly.

Dual Source Thermal Evaporation + In Situ Plasma Cleaning

Thermal evaporation deposition of Al and Ge from Tungsten and Tantalum boats, respectively. A blind hole is drilled and tapped in the chamber bottom plate for a center tap feedthrough (common ground) for the boats. Deposition starts at around 7e-7Torr and ends around 5e-6Torr due to outgassing. Aluminum alloys with Tungsten at the high temperature and causes boat failure, a thicker gauge boat will be used in the future or one made of TiB2-BN or BN. Update: W 0.015″ boat thickness seems OK.

Approx. deposition rate throughout the run was 2.2A/s, with total accumulation of 500A. Much faster than my sputtering setup but yields a worse film.

In situ plasma cleaning is via the red ICP coil seen in the 8th picture. A Quartz Crystal Microbalance (QCM) is used to measure the thickness of the deposited films and current is supplied by a rewound microwave oven transformer. The UV-VIS spectrometer is used to monitor the emission spectra of O2 plasma. O2 is flowed into the chamber via a Mass Flow Controller (MFC) until the pressure is 75-100mTorr and the substrate is plasma cleaned for 5 minutes with 100W RF prior to depositions.

As current pass through the boats, they heat up to 1000 – 1800C and subsequently heat up much of the surrounding chamber and mounting parts. This starts serious outgassing in the chamber and without prior cleaning and bake out quickly raises the pressure to non-workable pressures and the deposition rate slows.

I added a second turbo pump to raise the pumping speed/gas throughput (previously 110L/s and now an additional 50L/s) and to tolerate higher outgassing.

It was also noted that the evaporation of Al with lots of H2O vapor in the chamber (no baking) leads to a reduction of chamber pressure (presumably the formation of Al2O3 with H2O) and the production of H2 as seen on an RGA.

Developing Patterning Process for Homemade Microelectronics


Final process:

  • Clean/prep wafer – Piranha, RCA 1 / 2
  • Water rinse
  • Remove native and RCA oxide – 1-2% HF dip
  • Field oxide growth – 2 hours @ 1200 c w/ water vapor, 5000A blue film
  • If wafer in storage, dehydration bake – 10 min @ 220c
  • Check wafer hydrophobic if necessary
  • Optional spin HMDS
  • Spin 3.5mL AZ 4210 resist 30 sec @ 3500 rpm ~3.5um film
  • Soft bake resist 3 min @ 105c hotplate
  • Expose active area – 18 sec DLP projector
  • Develop 1:3 400k KOH:H20 puddle 2 min
  • Water rinse (no solvent)
  • Inspect wafer, if defect strip resist and retry
  • Hard bake 5 min @ 115c hotplate
  • Etch active area – 1-2% HF 10 min or until surface hydrophobic
  • Water rinse
  • Resist strip – Plasma ashing 100 watts RF 5 min @ 125mTorr O2
  • Acetone rinse
  • IPA rinse
  • Water rinse

Tall particles can easily short out the thin gate oxide in these devices, as shown under my SEM. This poses an issue for making such devices in a garage; the gate oxides must be grown thicker to mitigate shorted devices which leads to a higher threshold voltage for the FET.

Developing Metalization Process for Homemade Microelectronics

(Click on image to enlarge)

Progress in developing the metalization process for the home chip lab. DC and RF sputtering is used and the process will be refined more and then I will move on to the wet process with etching metal through resist mask, etc.

Sputtering Setup

Sample is scratched with a razor and surface roughness is measured with a KLA Tencor Stylus Profiler. Surface is extremely rough and best interpretation of the data leads me to believe the thickness of the sputtered film is approximately 0.492um.

DC Sputtering
DC Sputtering

Maskless Photolithography

Update 8/26/17: Developing Patterning Process for Homemade Microelectronics

The general idea is to use a modified presentation projector and reduction optics to transfer an image to the photoresist on a wafer without the use of expensive masks. Below are descriptions of the 4 iterations of my photolithography setups:

Mark IV:

Automated DLP submicron stepper for 2″ (50mm) wafers with LabView control, computer alignment, and wafer vacuum chuck

Stepped array
Stepped array

The second and third images above are composed of 4 precisely aligned exposures which enables submicron resolution over large areas. This “true” stepper operation uses a closed-loop feedback system and computer visual alignment.

SEM image
SEM image

Mark III:

Manual LCoS submicron stepper with red laser alignment illumination. Given a numerical aperture of 0.98 on the microscope objective and with an exposure wavelength of 365nm the simple calculated resolution is 0.227um however the actual resolution is probably around 0.5um due to diffraction limitations inherent in this projection system. The depth of focus @ NA = 0.98 is calculated to be approximately 1.8um but is likely worse.

Mark II:

Manual DLP projection aligner >10um features. Color wheel is removed because it did not transmit much light below 400nm. Emulation (relaxation oscillator) circuits were made to reproduce the signals that the projector expected from the color wheel back EMF motor drive/sensor and photodiode.

Exposure times calculated by integration of total UV dosage measured at different wavelengths with the radiometer. To calculate exposure time for AZ4210 resist, for example, the datasheet is consulted to see a recommended dose of around 135 mJ/cm^2 for a 3.5um film thickness. If exposed with a 5x objective on my system, the exposure time @ 410nm is (135 mJ/cm^2)/(4.05mW/cm^2) = approx. 33 seconds. This is a bit longer than I would like but given that it is a positive resist that is to be expected.


Mark I:

Proof-of-concept DLP setup