Fabrication and Characterization of N-Channel Enhancement Mode Insulated Gate Field Effect Transistors

nmos fet fabrication

Intro to Semiconductor Fabrication_D7V6867 _D7V6866Nmos fet construction_D7V6896_D7V6898_D7V6900_D7V6901IMG_9239IMG_9238IMG_9233IMG_9232IMG_9231

These are my first working transistors. Specifically, they are insulated gate enhancement mode n channel field effect transistors. I also made a depletion mode FET with a conducting channel and it worked even better than the enhancement mode ones. I drew out the steps I took to make this, they’re based on Jeri Ellsworth’s work but with a few main changes. She made no mention of it in her videos but it is very important that your dielectric overlap source and drain regions on the FET, otherwise no inversion layer can be formed and the FET cannot turn on. Only a small overlap is necessary and the larger it is, the more unwanted capacitance there is. I will make YouTube videos as soon as I have time that go into more detail about how I made it and also show the device’s characteristics.

A huge thanks to Jeri for making her videos about home chip fabrication which got me interested in these experiments in the first place.

You can see in the center of the transistor there is a red region of silicon dioxide, this is the gate and the color indicates that it is roughly 750 angstroms thick. I would like to make the gate thinner so I can achieve lower threshold voltages, etc. but it is hard to make a truly insulating gate much thinner than that in a dirty environment because of pinholes and other impurities in the oxide layer.


Step by step fab video

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