There are a number of open source layout and design tools for ICs however here I will just focus on Magic VLSI. Below are the steps to take a design from Verilog through synthesis and layout to the physical mask that is used for fabrication, via the Qflow digital synthesis flow.

The Verilog digital design for this example is a UART interface from www.asic-world.com and is synthesized/routed with the standard SCMOS rules, however a custom .tech file can be specified containing process details and design rules for DRC.

Once Qflow executes successfully, the design can be viewed in Magic after loading the appropriate cells and a GDS file is generated. This is opened in OwlVision GDSII Viewer or similar which can be used to generate the individual mask image files for each layer (active, poly, metal, etc.)

Using the same tools mentioned above, I also designed a simple PMOS chip to test my process. It is scalable to any reasonable size and contains 2 differential amplifier circuits (seen on right and middle) and a number of diodes/resistors and other test features on the left.

The design requires 4 masks for fabrication: active/diffusion, gate oxide, contact, and metal.

Fiducials should be added for subsequent layer alignment. Note: Grateful Dead bears are necessary for the circuit to function correctly.

Final process:

• Clean/prep wafer – Piranha, RCA 1 / 2
• Water rinse
• Remove native and RCA oxide – 1-2% HF dip
• Field oxide growth – 1200 c w/ water vapor, 5000A blue film
• If wafer in storage, dehydration bake – 10 min @ 220c
• Check wafer hydrophobic if necessary
• Optional spin HMDS
• Spin 3.5mL AZ 4210 resist 30 sec @ 3500 rpm ~3.5um film
• Soft bake resist 2 min @ 105c hotplate
• Expose active area
• Develop 1:3 400k KOH:H20 puddle 1 min
• Water rinse (no solvent)
• Inspect wafer, if defect strip resist and retry
• Hard bake 15 min @ 125c hotplate
• Etch active area – 1-2% HF 15 min or until surface hydrophobic
• Water rinse
• Resist strip – Acetone or plasma ashing 100 watts RF 5 min @ 125mTorr O2
• IPA rinse
• Water rinse

Tall particles can easily short out the thin gate oxide in these devices, as shown under my SEM. This poses an issue for making such devices in a garage; the gate oxides must be grown thicker to mitigate shorted devices which leads to a higher threshold voltage for the FET.

(Click on image to enlarge)

Progress in developing the metalization process for the home chip lab. DC and RF sputtering is used and the process will be refined more and then I will move on to the wet process with etching metal through resist mask, etc.

Sputtering Setup

Sample is scratched with a razor and surface roughness is measured with a KLA Tencor Stylus Profiler. Surface is extremely rough and best interpretation of the data leads me to believe the thickness of the sputtered film is approximately 0.492um.

Update 8/26/17: Developing Patterning Process for Homemade Microelectronics

The general idea is to use a modified presentation projector and reduction optics to transfer an image to the photoresist on a wafer without the use of expensive masks. Below are descriptions of the 4 iterations of my photolithography setups:

Mark IV:

Automated DLP submicron stepper for 2″ (50mm) wafers with LabView control, computer alignment, and wafer vacuum chuck

The second and third images above are composed of 4 precisely aligned exposures which enables submicron resolution over large areas. This “true” stepper operation uses a closed-loop feedback system and computer visual alignment.

Issues with non-uniform UV intensity across the exposure field were corrected by applying a mask to each projected image, described here. Proper results were achieved through many trials of different parameters:

Mark III:

Manual LCoS submicron stepper with red laser alignment illumination. Given a numerical aperture of 0.98 on the microscope objective and with an exposure wavelength of 365nm the simple calculated resolution is 0.227um however the actual resolution is probably around 0.5um due to diffraction limitations inherent in this projection system. The depth of focus @ NA = 0.98 is calculated to be approximately 1.8um but is likely worse.

Mark II:

Manual DLP projection aligner >10um features. Color wheel is removed because it did not transmit much light below 400nm. Emulation (relaxation oscillator) circuits were made to reproduce the signals that the projector expected from the color wheel back EMF motor drive/sensor and photodiode.

Exposure times calculated by integration of total UV dosage measured at different wavelengths with the radiometer. To calculate exposure time for AZ4210 resist, for example, the datasheet is consulted to see a recommended dose of around 135 mJ/cm^2 for a 3.5um film thickness. If exposed with a 5x objective on my system, the exposure time @ 410nm is (135 mJ/cm^2)/(4.05mW/cm^2) = approx. 33 seconds. This is a bit longer than I would like but given that it is a positive resist that is to be expected.

Mark I:

Proof-of-concept DLP setup

 

Sulfuric Acid Dilution Procedure PDF

Home Chip Fab

Plasma/Ion Source

Maskless Photolithography

Scanning Electron Microscope

Rewound a microwave oven transformer using 1 gauge welding wire. Before saturation it puts out 1.8volts ish. I plan to use it to heat up a tungsten boat for thermal evaporation deposition. I may rewind it with slightly thinner wire so I can get more turns on the secondary and a little higher voltage. Last picture is a new/old Lindberg 1″ dia. tube furnace I got, goes up to 1400c which is crazy. I use it for diffusion of N type and P type dopants into my homemade semiconductors as well as thermal oxidation. I have a large nitrogen tank which allows me to create a nitrogen atmosphere in it during diffusion and when I want to facilitate SiO2 growth I pump steam through the furnace and turn the nitrogen flow off. I have a mass flow controller for the nitrogen but haven’t hooked it up yet.

Update 4/25/18: First IC!

Update 8/27/17: Developing Patterning Process for Homemade Microelectronics

Update 7/30/17: Developing Metalization Process for Homemade Microelectronics

These are my first working transistors. Specifically, they are insulated gate enhancement mode n channel field effect transistors. I also made a depletion mode FET with a conducting channel and it worked even better than the enhancement mode ones. I drew out the steps I took to make this, they’re based on Jeri Ellsworth’s work but with a few main changes. It is very important that your dielectric overlap source and drain regions on the FET, otherwise no inversion layer can be formed and the FET cannot turn on. Only a small overlap is necessary and the larger it is, the more unwanted capacitance there is. This is not normally a consideration in actual production because inherent lateral diffusion takes care of the overlap but for these large hand made devices I found you have to get very lucky with your alignment if you don’t budget extra overlap.

A huge thanks to Jeri for making her videos about home chip fabrication which got me interested in these experiments in the first place.

You can see in the center of the transistor there is a red region of silicon dioxide, this is the gate and the color indicates that it is roughly 750 angstroms thick. I would like to make the gate thinner so I can achieve lower threshold voltages, etc. but it is hard to make a truly insulating gate much thinner than that in a dirty environment because of pinholes and other impurities in the oxide layer.

Diode characteristics are characterized with a semiconductor parameter analyzer

A brief introduction to semiconductor fabrication processes and terminology. It is not intended to be an in depth view of any single process, but rather an overview so that provides enough information for someone to get started with making diodes and transistors at home.

Tour of my home chip fab setup in early 2017. I’ve been accumulating this equipment since October of 2016.

Step by step FET fabrication